FIG. 1 is a graph which shows a relationship between a voltage V applied to terminals a and b of a ferroelectric capacitor and induced charges Q of a ferroelectric capacitor. The "ferroelectric capacitor" means a capacitor which uses ferroelectric materials as dielectric materials. As shown in FIG. 1, a ferroelectric capacitor has the hysteresis characteristic.
When the applied voltage V is 0 volt, the amount of induced charges Q is either "A" or "B". Therefore, the ferroelectric capacitor can store binary data without power supply. Because of those properties, the ferroelectric capacitor has been used in the memory cells of a nonvolatile memory device.
The amount of induced charges Q of the ferroelectric capacitor changes according to the applied voltage V. For example, when a sufficient negative voltage is applied to the ferroelectric capacitor and the ferroelectric capacitor is in the polarization state "A" shown in FIG. 1, the polarization state changes to state "C" shown in FIG. 1. Then, if this negative voltage is removed, the polarization state changes to state "B" shown in FIG. 1. The variation in the amount of induced charges .DELTA.Q induced by the applied voltage V can be interpreted as digital data of the memory cell.
It is already known to those having ordinary skill in the art that the ferroelectric capacitor has "fatigue" phenomenon due to the repeated switching of polarization state of the ferroelectric material according to the change of the applied voltage V. FIG. 2 shows the hysteresis curves 20 and 30 of the non-fatigued, i.e. original ferroelectric capacitor and the fatigued ferroelectric capacitor. As shown in FIG. 2, the variation in the amount of induced charges in the non-fatigued ferroelectric capacitor from point "A" to point "B" is .DELTA.Q.sub.R1, while that of the fatigued ferroelectric capacitor is .DELTA.Q.sub.R2, which is smaller than .DELTA.Q.sub.R1. So, the sensing margin for the data from a fatigued ferroelectric capacitor is smaller than that from a non-fatigued ferroelectric capacitor, and the reliability of the memory device is also reduced. Further, because of the fatigue phenomenon of the ferroelectric capacitor, the life time of the ferroelectric memory is generally shorter than that of the DRAM or SRAM.
FIG. 3 shows a hysteresis curve of a ferroelectric capacitor used as a data storage means. When the polarization state of the ferroelectric capacitor is "A", it is defined that the "1" data is stored in the ferroelectric capacitor, and when the polarization state of the ferroelectric capacitor is "B", it is defined that the "0" data is stored therein. In case the initial polarization state of the ferroelectric capacitor is "A", as a "-V1" voltage is applied to the ferroelectric capacitor, the polarization state of the ferroelectric capacitor moves to "C" and the variation in amount of the induced charges will be .DELTA.Q1 in FIG. 3. On the other hand, in case the initial polarization state of the ferroelectric capacitor is "B", as a "-V1" voltage is applied to the ferroelectric capacitor, the variation in amount of the induced charges will be .DELTA.Q0 in FIG. 3. This variation in the amount of induced charges .DELTA.Q1 or .DELTA.Q0 results in a change of a precharged voltage on a bit line by means of charge sharing of the ferroelectric capacitor with the bit line capacitor in a memory cell array. The changed voltage of the bit line is sensed and amplified by sense amplifier and becomes a digital data. In general, the sense amplifier needs a reference voltage to sense and amplify the voltage on the bit line. The reference voltage has a value which is in the middle of the voltages generated by the induced charges when the ferroelectric memory stores "1" data or "0" data. The reference voltage is generated by a dummy cell having ferroelectric capacitor.
FIG. 4 is a circuit diagram of a portion of a conventional ferroelectric memory device having a conventional reference voltage generating circuit (published by IEEE Journal of Solid State Circuits, Vol. 31, No. 11, November 1996). The conventional ferroelectric memory device includes a sense amplifier S1 for sensing a small voltage difference between bit lines BL and BLB, a memory cell array M1 including a plurality of memory cells each of which has a switching transistor and a ferroelectric capacitor, a reference voltage generating circuit R1 for generating a reference voltage and a precharge circuit P1 for precharging the bit lines BL and BLB to a ground voltage level.
As shown in FIG. 4, the memory cell array M1 of the ferroelectric memory device is configured as a matrix with a plurality of word lines and bit lines crossing one another. The source of the switching transistor of the memory cell is coupled to the bit line BL, and the gate of the switching transistor is coupled to the word line WL0 or WL1. The one side of the ferroelectric capacitor of the memory cell is coupled to the drain of the switching transistor, and the other side of the ferroelectric capacitor is coupled to the bit bar line BLB (which is also referred to as "plate line").
Now, the operation of the reference voltage generating circuit R1 is described in detail. First of all, "1" and "0" data are respectively stored in dummy cells RS0 and RS1. In order to read the data stored in the dummy cells RS0 and RS1, the reference word line RWL is enabled to turn on the switching transistors RT0 and RT1 of the dummy cells RS0 and RS1, and the reference plate line RCP is driven to a "High" voltage level so that a negative voltage is applied to the ferroelectric capacitors of the dummy cells RS0 and RS1. As a result, voltages generated by the variations in the amount of induced charges .DELTA.Q1 and .DELTA.Q0 are transferred to the reference voltage lines RL and RLB, respectively. Then, the REQ signal is drived to a "High" level so that the reference voltage lines RL and RLB are equalized. Then, the DT or /DT signal is driven to "High" so that the voltage on the reference voltage line is transferred to the bit lines BL or BLB in order to be used as a reference voltage.
However, since the above mentioned conventional reference voltage generating circuit generates the reference voltage by reading the dummy cells storing "1" or "0" data, the fatigue phenomenon is occurred in the ferroelectric capacitor of the dummy cells. Therefore, the generated reference voltage is subject to change as the ferroelectric material is fatigued. This is especially true when the reference voltage generating circuit is used for a plurality of memory cells because the number of read operation is much larger than that of the normal cells. Therefore, the lifetime of the ferroelectric memory device is shorten by the reference voltage generating circuit while the memory cells are still usable.